Clash: a functional hardware description language - Prelude library.
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.Support for multiple clock domains, with type safe clock domain crossing.
This package provides:
Prelude library containing datatypes and functions for circuit design
To use the library:
Import
Clash.PreludeAlternatively, if you want to explicitly route clock and reset ports, for more straightforward multi-clock designs, you can import the
Clash.Explicit.Preludemodule. Note that you should not importClash.PreludeandClash.Explicit.Preludeat the same time as they have overlapping definitions.
A preliminary version of a tutorial can be found in Clash.Tutorial, for a general overview of the library you should however check out Clash.Prelude. Some circuit examples can be found in Clash.Examples.
Clash - A functional hardware description language
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
Strongly typed, yet with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.Support for multiple clock domains, with type safe clock domain crossing.
Open-source community
Clash benefits from an active community. Whether you need a question answered or want to contribute to open-source features, browse the features below to make the most of Clash.