ice40-prim

Lattice iCE40 Primitive IP

Supported IP Modules

Ice40.Spram - For more information see the iCE40 SPRAM Usage Guide
- sysMem Single Port RAM Memory (SPRAM)
- Each block of SPRAM is 16k x 16 (256 kbits)
- 16-bit data width with nibble mast control
- Cascadable design for deeper/wider SPRAM
- Three power modes, standby, sleep, and power off
Ice40.Mac - For more information see the DSP Function Usage Guide PDF
- 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit multipliers
- Optional independent pipeline control on input Register, Output Register, and Intermediate Register for faster clock performance
- 32-bit accumulator, or two independent 16-bit accumulators
- 32-bit, or two independent 16-bit adder/subtractor functions, registered or asynchronous
- Cascadable to create wider accumulator blocks
Ice40.Osc - For more information see the iCE40 Oscillator Usage Guide
- on-chip oscillator
- Low-power low frequency oscillator of 10 kHz
- High frequency oscillator configurable to 48 Mhz, 24 Mhz, 12 Mhz, or 6 Mhz
- See also Ice40.Clock for clock domains and reset
Ice40.Pll - For more information see the iCE40 sysCLOCK PLL Design and Usage Guide
- Pad and Core variants
- Phase Lock Loop (PLL)
- Provides a variety of user-synthesizable clock frequencies along with custom phase delays
- Generates a new output clock freuquency via clock multiplication and division
- De-skews or phase-aligns an output clock to the input reference clock
- Corrects output clock to have nearly a 50% duty cycle, which is important for Double Data Rate (DDR) applications
Ice40.Rgb - For more information see the iCE40 LED Driver Usage Guide
- RGB High Current Drive I/O Pins
- Provides sinking current to an LED connecting to the positive supply
- Three outputs designed to drive the RGB LEDs
- RGB drive current is user programmable from 4mA to 24mA, in increments of 4mA
Ice40.Led - For more information see the iCE40 LED Driver Usage Guide PDF
- LED PWM IP
- Provide easier usage of RGB high current drivers
- Provides flexibility for user to dynamically change the modulation width of each of the RGB LED driver
- User can dynamically change ON and OFF-time durations
- Ability to turn LEDs on and off gradually with breath-on and breath-off time
Ice40.Spi - For more information see the Advanced SPI and I2C Usage Guide PDF
- User SPI IP
- Configurable Boss and Worker modes
- Full-Duplex data transfer
- Mode fault error flag with CPU interrupt capability
- Double-buffered data register
- Serial clock with programmable polarity and phase
- LSB First or MSB First data transfer
Ice40.IO
- IO primitive
Ice40.GB
- Global buffer primitive
- Required for a user's internally generated FPGA signal that is heavily loaded and requires global buffering; for example, a user's logic-generated clock
Ice40.I2c - For more information see the Advanced SPI and I2C Usage Guide PDF
- User I2C IP
- Boss and Worker operation
- 7-bit and 10-bit addressing
- Multi-master arbitration support
- Clock stretching
- Up to 400 kHz data transfer speed
- General Call support
- Optionally delaying input or output data, or both
- Optional filter on SCL input