RISC-V Core.

Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.

Where Lions Roam: RISC-V on the VELDT

Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.

This repository contains four parts:

1. The Lion library: a pipelined RISC-V core.
2. lion-formal: formally verify the core using riscv-formal.
3. lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.
4. lion-metric: Observe Yosys synthesis metrics on the Lion Core.

Lion library

Usage:

1. Add lion to build depends section of Cabal file
2. import module in source files import Lion.Core

When connecting the core to memory and peripherals, ensure single cycle latency.

Clone the repository

1. git clone https://github.com/standardsemiconductor/lion.git
2. cd lion
3. git submodule update --init

Features

Current Support

• Architecture: RV32I (no FENCE, ECALL, EBREAK)
• Configurable ALU adder and subtractor: use a generic (+) and (-) or SB_MAC16 hard IP

Future Support

All features will be added in a configurable manner extending the base RV32I configuration noted above

• Zicsr, Control and Status Register (CSR) Instructions
• CSR registers
• RV32IM

Check out the Lion Development project to see which features are in progress.

References and Additional Resources

• RISC-V Specifications
• Computer Architecture: A Quantitative Approach 6th Ed.