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Description

Verilog preprocessor, parser, and AST.

A parser and supporting a small subset of Verilog. Intended for machine generated, synthesizable code.

Metadata

Version

0.0.11

Platforms (75)

    Darwin
    FreeBSD 13
    Genode
    GHCJS
    Linux
    MMIXware
    NetBSD
    none
    OpenBSD
    Redox
    Solaris
    WASI
    Windows
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